The present invention relates to a solid state image sensor, and more particularly to a solid state image sensor of the line addressing type.
A typical solid state image sensor of the line addressing type, in which a device according to the present invention is included, is shown in FIG. 1. Photoelectric cells 1 are arranged in a two-dimensional matrix manner (four rows, two columns, in this example). Charges produced in respective cells 1 are read out to a vertical transfer section 3 through address gates 2. This read operation is carried out using addressing pulses delivered from an address scan circuit 4. Such a read operation is conducted in connection with only an addressed row. A charge which has been read to the vertical transfer section 3 is transferred to the lower direction in this figure by an n-phase transfer clock (two-phase clock comprising .phi..sub.1 and .phi..sub.2 in the example shown in FIG. 1). The charge is transferred to bottom electrodes 6 through temporary storage electrodes 5, and is further transferred to a horizontal transfer section 7. The charge on the horizontal transfer section 7 is transferred to the left in the figure and then is taken out from an output circuit 8.
FIGS. 2(a) to 2(d) are explanatory views showing the sequence of the conventional transfer operation of the solid state image sensor configured as stated above. FIGS. 3(a) to 3(d) are time charts for this transfer operation. First, when the first addressing operation is executed at time t.sub.1 as shown in FIG. 3(b), a charge S1 is read out to the vertical transfer section 3 as shown in FIG. 2(a). Subsequently, the charge S1 is stored in the temporary storage electrode 5 for a predetermined time interval by clocks .phi..sub.1 and .phi..sub.2 shown in FIGS. 3(c) and 3(d). Then, the charge S1 thus stored is transferred to the horizontal transfer section 7 via the bottom electrode 6. In a manner similar to the above, the second, third and fourth addressing operations are executed at times t.sub.2, t.sub.3 and t.sub.4, respectively. Thus, charges S2, S3 and S4 are read out as shown in FIGS. 2(b), 2(c) and 2(d), respectively. In this example, respective addressing cycles T.sub.a1 to T.sub.a3 are the same. On the other hand, the transfer operation in the horizontal transfer section 7 is carried out in accordance with the row scanning cycle shown in FIG. 3(a). Namely, the charge S1 is transferred on the horizontal transfer section 7 for the first row scanning period beginning from time t.sub.5 and is then taken out from the output circuit 8. Similarly, the charges S2, S3 and S4 are transferred for the second, third and fourth row scanning periods beginning from times t.sub.6, t.sub.7 and t.sub.8, respectively. The respective row scanning cycles T.sub.s1 to T.sub.s4 are the same and blanking periods are provided in the respective row scanning cycles. It is to be noted that the addressing cycle T.sub.a must be smaller than the row scanning cycle T.sub.s. This is because times required for transferring the charges S1 and S4 to the position of the bottom electrode 6 on the vertical transfer section 3 are different from each other. For instance, the charge S4 must be reached to the horizontal transfer section 7 until time t.sub.8. Accordingly, it is required that the transfer of the charge S4 is carried out for a time period from time t.sub.4 of the fourth addressing time to time t.sub.8 by taking a time margin corresponding thereto into account.
However, the drawback with the device which performs the above-mentioned transfer operation is that noise components are superimposed on a signal taken out from the output circuit 8. Such noise components are produced in the addressing operation for reading charges to the vertical transfer section 3 and the operation for transferring charges on the vertical transfer section 3 due to the fact that a pulse voltage applied to each electrode is mixed into an output signal by capacitive coupling. Since such addressing and transfer operations are continuously carried out within a row scanning period as seen from the time chart in FIG. 3, noise mixing cannot be avoided with the conventional device, with the result that only an image having low S/N ratio can be obtained.
To solve such a problem, an attempt is made to complete the above-mentioned addressing and the transfer operations within the blanking period. However, this blanking period is extremely small as compared to the row scanning time as shown in FIG. 3(a). For example, for transferring the charge S4, which is located farmost position, to the horizontal transfer section 7 within this blanking period, a considerable fast transfer speed is required. Particularly, in a large scale device provided with the vertical transfer section having a number of transfer stages, the load capacity of the electrode terminal is in the order of several hundred to several thousand pF. Thus, an extremely large power energy is required for carrying out high speed transfer, resulting in loss of practicability.
On the other hand, a technique to cause the addressing cycle and the row scanning cycle to be in correspondence with each other to solve the above-mentioned problem is disclosed by the inventor of the present invention in the Japanese Patent Publication bearing application No. 206679/1981. The detail of this technique should be referred to the above-mentioned publication and therefore its explanation is omitted here. The drawback with this technique, however, is that all the transfer stages are filled with signal charges according as addressing operations are repeated, thus making it difficult to drain unnecessary charges produced during the vertical transfer operation, resulting in lowered S/N ratio.